1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that delays a pulse signal from an ATD (Address Transition Detection) buffer to generate a word line activation signal.
2. Description of the Background Art
In the semiconductor memory device referred to as asynchronous SRAM (Static Random Access Memory), ATD buffers are provided at various places that generate a one-shot pulse signal according to change of an address signal, a chip select signal, a read/write enable signal, and an input data signal. A word line activation signal WLE is generated by a timing generator that delays the trailing edge of a pulse signal supplied from the ATD buffer as illustrated in FIG. 17.
A pulse signal LATD1 input to the timing generator is generated in response to change of a row address signal by an ATD buffer provided for a row address buffer, and an ATD signal LATD2 is generated in response to change of a column address signal by an ATD buffer provided for a column address buffer. FIG. 18 is a block diagram illustrating a structure of an address buffer (row address buffer or column address buffer). The address buffer generates internal address signals A and /A in response to an external address signal EAD when a chip select signal /CS is active (at a logical low level), and an address signal atd is supplied to a corresponding ATD buffer.
Word line activation signal WLE is supplied to a row decoder shown in FIG. 19. The row decoder selectively activates word lines WL1-WL4 in response to internal address signals A1, /A1, A2, and /A2 when word line activation signal WLE is active (at a logical high level).
The timing generator generally includes multiple stages of delay circuits RDLs as shown in FIG. 17. The pulse width of a signal output from delay circuit RDL remarkably increases as the power supply voltage decreases as indicated by (2) of FIG. 20.
FIGS. 21A-21R represents internal waveforms of the SRAM in the case that the power supply voltage is relatively high. Referring to FIGS. 21A-21R, if the power supply voltage is high, the pulse width of delay circuit RDL is relatively small, and the pulse width of word line activation signal WLE is accordingly in the range of an address cycle. In this case, even if there is skew between internal address signals A1 and A2 to cause nodes N2 and N3 corresponding to non-selected addresses to rise, word lines WL2 and WL3 corresponding to the skew addresses do not rise since word line activation signal WLE is at a logical low or L level.
The current trend of miniaturization and reduced voltage of a semiconductor memory device requires that the operation of the memory device is ensured on one chip in a range of a higher supply voltage to a lower supply voltage.
The internal waveforms of the SRAM represented by FIGS. 21A-21R in the case of the higher supply voltage change to those internal waveforms represented by FIGS. 22A-22R if the supply voltage of the SRAM is low. As the supply voltage decreases, the pulse width of the pulse signal output from delay circuit RDL remarkably increases as shown in FIG. 20. Therefore, the pulse width of word line activation signal WLE exceeds the address cycle and word line activation signal WLE is fixed at a logical high or H level.
In this case, if there is skew between internal address signals A1 and A2, nodes N2 and N3 corresponding to non-selected addresses rise. Word line activation signal WLE fixed at H level thus causes word lines WL2 and WL3 corresponding to skew addresses, in addition to selected word lines WL1 and WL4, to rise.
Since word lines WL2 and WL3 corresponding to the skew addresses rise, it follows that data could be read at this instant from memory cells corresponding to the skew addresses, to delay access to a memory cell corresponding to a selected address. Further, in the case of the write cycle, writing could be done wrongly.